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Talk about the application of FPGA and USB technology in textile digital printing machine

the industrial textile digital printing machine system is divided into two parts: the printing machine and the upper master PC. the textile printing machine is not an independent system. It is a device that receives the instructions and image data of the upper master PC, completes the printing action according to the instructions and image data, and feeds back its working state to the upper master PC. The interface part is the bridge to realize the communication between the front-end controller in the printing machine and the upper master PC

in the real-time industrial field, the textile digital ink-jet printer requires a high transmission speed. The communication between the traditional digital ink-jet printer and the host is mainly realized through the serial interface, parallel interface or interface card provided by the host motherboard. Because of its low transmission speed, it can no longer meet the needs of high-speed industrial production process. USB technology solves the above problems well. Although the recently released USB3.0 protocol can theoretically reach the limit transmission speed of 5 gb/s, the microprocessor integrated with USB3.0 is still in the experimental stage and needs to be released to the market after comprehensive optimization. Therefore, the microprocessor supporting USB2.0 protocol is still the main communication microprocessor selected in the industrial high-speed printing and dyeing equipment

fpga is a field programmable gate array electronic integrated device. Due to its high integration, several large printed circuit boards realized by small and medium-sized integrated circuits are reduced to oneortwo very large-scale integrated circuits, which not only greatly reduces the volume of the control system, but also greatly improves the reliability of the system. The programmability of FPGA can also make the design, debugging, production and maintenance of the control system of textile digital printing machine more flexible and convenient. With the rapid development of large-scale programmable logic device FPGA, FPGA devices can play a superior performance and greater role in such a motion control system. As an auxiliary circuit of the control system of textile digital printing machine, it can replace many traditional logic circuits, simplify the system design, improve the reliability of the system, reduce the size of the circuit board, miniaturize the products, and protect intellectual property rights [1]. How to optimize the transmission performance of USB2.0 equipment, break through the speed bottleneck and maximize the transmission speed is an urgent problem to be solved in the design of printing press. This paper designs the data transmission system of high-speed industrial textile digital ink-jet printer based on USB2.0, and then studies the design optimization of FPGA in the printer system and the method of realizing the overall improvement of USB2.0 interface data transmission speed

1 system design

according to the characteristics of the textile printing machine system, this system can be controlled by a PC, using IJA mode inkjet printer nozzle, each nozzle 510 holes, 180 DPI. In order to improve the printing speed, group nozzles are used, with 6 or 8 colors in each group, and a total of 3-6 groups are available. It supports printing images with 1~4 gray levels. The main controller of the system is composed of data transmission board and motion control board, mainly composed of ARM core board with S3C2440 as processor, 400 MHz working frequency, 64 MB SDRAM, 16 MB flash, LCD interface, IIC interface, 16 bit external bus addressing and DMA. The main controller receives the control command and image data from the PC, detects and controls each movement link in the system, synchronizes the movement with the spray of the nozzle, and transmits the image data required by the nozzle to the nozzle board

when working online, the main controller should be able to communicate with PC in both directions, receive image data, various configuration information and control commands from PC, and transmit the system status to PC. USB2.0 interface protocol can be considered. Because S3C2440 does not support USB2.0 protocol, the system expands the USB expansion interface chip of CY7C68013A. In order to buffer the chip and arm bus, the system expands an FPGA. FPGA is responsible for USB interface buffer, motion control, position and speed detection, secondary ink cartridge liquid level detection, secondary ink cartridge liquid pump control, image data format conversion and transmission of nozzle board, and control of ignition nozzle according to nozzle position and color sequence

this paper mainly discusses the data communication between PC host and main control board of printing machine. In view of the requirements of the system, this communication module uses EZ-USB fx2lp single chip CY7C68013A, which supports USB2.0 high-speed data transmission, as the interface chip. FPGA ep1c6q-240 is used as the external logic of USB interface chip to complete the communication between FPGA and USB interface chip. When the upper computer sends a control signal, it communicates with FPGA after being analyzed by the interface chip CY7C68013A. When the main controller of the system detects the commands such as starting data transmission and selecting data format sent by the upper computer, it starts data transmission. The data packet parsed by Sie passes through the USB interface chip CY7C68013. The market supervision department will promote all localities and departments to increase the publicity of enterprise related charging matters. A in the mode of synchronous slave FIFO, the data is quickly stored in the FIFO inside the FPGA through the FIFO cache controlled by the internal ping pong of CY7C68013A, Then, the main controller arm controls the FPGA to read the data transmitted by the host through USB by the nozzle controller, and then distribute it to the 6-color nozzle

2 hardware design

2.1 USB interface part

the printing of textile digital printing machine is in behavioral units, and each line of printing process must be sprayed at a constant speed. At the end of each row, the nozzle trolley shall be accelerated, decelerated and reversed, and the cloth roll shall be rolled into the cloth for the next row of printing. Constant image data transmission rate is necessary for constant speed printing. The higher the requirements of printing speed, the higher the requirements of image data transmission speed. In this communication system, CY7C68013A chip is selected, and its architecture is EZ-USB fx2lp, which is a USB2.0 chip improved on the basis of FX2. It integrates an enhanced 8051 core and adopts a low-power design, which represents the leading level in the industry. It is a new generation of architecture that conforms to USB2.0 high-speed controller and is fully compatible with fx2[2]

in the front-end control system of PC and fx2lp, the built-in CPU of fx2lp is responsible for receiving the command from the upper PC to control the movement of the printer, and synchronizing the image data. The image data is sent to the nozzle through FPGA and arm, and commands the nozzle to do an ignition action at the appropriate time. If we use the traditional method, the built-in CPU of fx2lp directly addresses the image memory that stores the image data sent by the upper computer, and synchronously sends the image data and motion control to FPGA, and then FPGA cooperates with arm to control the nozzle ignition. These actions require complex instruction sequences, multiple memory accesses, and a lot of time. It is almost impossible to achieve a high data transmission rate

by analyzing the working mechanism of textile inkjet printing machine, it is found that the front-end control system does not need to understand the image data sent by the upper computer. The compression experiment is carried out on the pressure experimental machine. What it needs to do is to synchronize these image data and transmit the image data to the nozzle at the appropriate time. Therefore, image data can be accessed without the built-in CPU of fx2lp, and can be directly sent to the nozzle under the synchronization of CPU. Because EZ-USB FX2 provides a unique architecture, the CPU of EZ-USB is not on the data channel of USB host and external logic. In order to achieve the maximum data bandwidth, EZ-USB connects the USB host and mold temperature directly to the external logic, which is the main factor to control the cooling and finalization of products, so as to bypass the CPU, so that the USB interface and the external application environment can directly share the FIFO, and the microprocessor can not participate in the data transmission [4]. At this time, the data exchange between the endpoint FIFO and the outside can be directly realized without executing the internal 8051 firmware program of the USB interface chip, This processing architecture, called quantum FIFO, solves the bandwidth bottleneck caused by the forwarding mode of ordinary microprocessors [3]

through the above analysis, the system adopts a method of bypassing image data. The 4 K endpoint FIFO shared internally by CY7C68013A is used as the temporary memory of the image. The input endpoint of FIFO memory directly receives the image pixel data of USB host. The output endpoint data of FIFO memory is synchronously read by FPGA, and the read data is sent to the nozzle through the control instruction of arm and hardware channel. Therefore, the transmission speed of image data is no longer closely related to the memory addressing cycle of EZ-USB CPU, so this bypass fast path is used to realize the high-speed data transmission between PC and nozzle. The function of FIFO is also to establish a buffer between high-speed USB transmission and medium speed continuous printing demand

2.2 FPGA bridging part

since CY7C68013A chip is selected as USB2.0 interface chip, and the interface frequency of this chip is different from the bus timing of the main controller of the system, this chip cannot be directly connected with the bus of the main controller, so FPGA is considered as bridging, so it is necessary to interface this chip with the bus inside FPGA, consider the different data transmission rate, and establish USB data buffer inside FPGA, The buffer is composed of FIFO, which completes the information exchange with the main controller. At the same time, as the external control logic of the slave FIFO mode, FPGA provides USB chip selection, write data clock, endpoint selection and other signals to realize the control of data reading and writing

(1) interface with USB chip

fpga internal bus is a synchronous 32-bit bus, and the bus signal includes 11 bit address line addr and 32-bit data input data_ i. 32 bit data output data_ o. Write control input we, bus cycle signal CYC, latch signal STB, response signal output ACK, system clock signal CLK and system reset signal rst, byte selection signal sel

(2) selection and establishment of FIFO

since both ends of FIFO need to operate at different rates, the adopted FIFO works with different clocks and is written in USB_ Ifclk is the synchronization clock, and the reading is based on the system clock CLK_ I is the synchronization clock. The write request line SLRD is synchronized with the write clock. When the FIFO is not full and the USB chip is not empty, a write request is always generated. This ensures that FIFO automatically reads out the data in the USB chip, reducing the burden of software judgment

since FIFO modules with different clocks cannot automatically generate near full and near empty signals, a half full signal is used, which is obtained by reading the highest bit of the word rdusedw. In this way, as long as the capacity of FIFO is properly selected, arm can judge the half full signal. Once there is a half full signal, arm can no longer judge and read out half the capacity data in FIFO. Considering that the nozzle needs at least 1 KB of data for each injection, the FIFO is selected with a capacity of at least 16 bits and 2 kb. When arm detects that the FIFO is not half full, if the FIFO is not empty, it can still read data, but at this time, it is necessary to detect whether the FIFO is empty for each word read, and the reading rate cannot be very high

3 software design

3.1 USB firmware program

usb firmware is a program running on the microcontroller integrated in CY7C68013A. The EZ-USB FX2 development kit of cypress company provides users with a firmware function library (b) and firmware framework, both of which are developed based on Keil C51. When using the firmware framework for specific firmware development, the firmware framework has implemented initialization, re enumeration, power management and other functions. For users, they only need to add code at the reserved position of the firmware architecture to complete specific functions [4]

in the firmware program design of this system, the initial setting function TD is used_ Init() and descriptor table file dscr A51 completes the initialization of the system and endpoint configuration. In order to optimize the data transmission speed, the combination of two endpoints is configured to realize high-speed batch

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